1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a flash electrically erasable programmable read only memory (flash EEPROM) device and a fabrication method thereof.
2. Description of the Background Art
FIG. 1 illustrates a cell layout of a conventional semiconductor memory device.
A plurality of field oxide films 101 are formed on a semiconductor substrate 100. The field oxide films 101 correspond to non-active regions or device isolation regions. The regions except for the field oxide films 101 are active regions 102. A plurality of floating gates FG are formed vertically to the active regions 102. An insulation film (not shown) is positioned on the floating gate FG, and a control gate CG is formed in an identical direction to the floating gate FG. In addition, a source 103 and a drain 104 are respectively formed on the active regions 202 at both sides of the floating gate FG. A contact hole 105 for connecting a bit line BL to the drain region 104 is formed at a predetermined region of the drain 104. The bit line BL is positioned crossing the control gate CG, and connected to the drain 104 via the contact hole 105. Referring to FIG. 1, a dotted-lined inner structure provided with reference numeral 110 depicts a unit cell of a flash electrically erasable programmable read only memory (flash EEPROM).
FIG. 2 is a vertical-sectional view taken along Line II—II in FIG. 1, illustrating a unit cell of an ETOX (EPROM with Tunnel Oxide) type flash EEPROM. As shown therein, a tunnel oxide film 201 which is a gate oxide film of a floating gate is formed on a semiconductor substrate 200. A floating gate electrode 202 consisting of polysilicon, an interpoly dielectric film 203 and a control gate electrode 204 are sequentially stacked on the tunnel oxide film 201. A source 205 and a drain 206 are formed in the semiconductor substrate 200 at both sides of the floating gate electrode 202. The source 205 includes a first source layer 205a (n+ layer) which is relatively highly doped, and a second source layer 205b (n− source) which is a relatively lightly doped. Such a source is called a graded junction source. The drain 206 is a highly-doped layer (n+ layer), identical to the first source 205a. The reason why the conventional flash EEPROM device employs the above asymmetric structure of the source (n−/n+ structure) and the drain (p+/n+ structure) will now be described.
During a programming operation of the flash EEPROM, a high voltage of 8V is applied to the drain, and a high voltage of 12V is applied to the gate electrode. A hot electron, generated in the drain, passes through the tunnel oxide film, and enters the floating gate. Accordingly, generation of the hot electron is facilitated by forming an abrupt junction of n+/p+ between the drain and substrate, thereby improving programming speed. In addition, a high voltage (over 10V) is applied to the source during an erase operation, thereby emitting the hot electron from the floating gate to the source. Here, in order for the source junction to endure the latter high voltage, a doping concentration of the n-type source is slowly decreased. The above-described flash memory cell has a disadvantage in that the cell's area is increased due to lateral diffusion of the source.
Accordingly, a method of applying a negative voltage to the gate electrode and applying a voltage below 5V to the source is conventionally practiced in order to restrict increase of the cell area resulting from the lateral diffusion and to improve reliability of the source junction. The flash memory of the aforementioned structure does not require a deep and slow junction structure (graded junction structure) like the ETOX memory as shown in FIG. 1. Therefore, the increase of the cell area resulting from the lateral diffusion of the source can be restricted. However, an overlap between the floating gate and the source region is necessary during the erase operation. In addition, the doping concentration of the source region must be sufficiently high to prevent a voltage drop by the source voltage during the program operation. For example, when the source is formed, the doping is below 2*1015 atom/cm2, a depletion layer is formed at an overlapping region with the floating gate. This results in tunneling, thereby sharply decreasing gate current. As a result, although the modified source structure does not require the graded junction structure, an asymmetric structure is formed where the source and drain have different doping concentrations.
A fabrication method of the flash memory device as shown in FIGS. 1 and 2 will now be described with reference to FIGS. 3A to 3E. FIGS. 3A to 3E illustrate sequential steps of the fabrication process of the flash memory device which are vertical-sectional views taken along Line IIIe—IIIe in FIG. 1 at their left side, and illustrate sequential steps of the fabrication process of a peripheral circuit unit of the flash memory device at their right side.
Referring to FIG. 3A, a device isolation region 301, namely a field oxide film 301 is formed on a semiconductor substrate 300 according to a well-known partial silicon oxidation process. The regions, except for the field oxide films 301 are active regions 301, and the regions of the field oxide films 302 are non-active regions. Here, the field oxide film is shown merely at the right side of FIG. 3A because the left side thereof illustrates the vertical-sectional view taken along Line IIIe—IIIe in FIG. 1.
As illustrated in FIG. 3A, a tunneling oxide film 303 is formed at a predetermined region of the semiconductor substrate 300 where a flash memory cell unit will be formed. Thereafter, a first polysilicon layer is formed on the tunneling oxide film 303, and patterned in order to remain merely at the active region 302, thereby forming a first polysilicon layer pattern 304. An interpoly dielectric film 305 consisting of an oxide film/nitride film/oxide film structure (hereinafter, referred to as ‘ONO film’) is formed on the resultant structure of the semiconductor substrate 300. The ONO film 305 serves to insulate the floating gate and the control gate, and becomes a gate insulation film of the control gate to be formed in a succeeding process. As shown at the right side of FIG. 3A, the ONO film 305 on the semiconductor substrate of the peripheral circuit unit is removed.
Then, a cleansing process is carried out. As illustrated at the right side of FIG. 3B, the entire surface of the semiconductor substrate is thermally oxidized, thereby forming a gate oxide film 306 on the semiconductor substrate 300 of the peripheral circuit unit.
As depicted in FIG. 3B, a second polysilicon layer is formed on the entire surface of the semiconductor substrate 300. The second polysilicon layer, the ONO film 305 and the first polysilicon layer pattern 304 are etched by using a known stack gate etching process, thereby forming a second polysilicon layer pattern 307a, namely a control gate electrode 307a, and a floating gate electrode 304a which is self aligned with the control gate electrode 307a, patterned, and positioned therebelow. The floating gate electrode 304a is formed by patterning the first polysilicon layer pattern 304 according to the stack gate etching process. Here, referring to the right side of FIG. 3B, a gate electrode 307b is also formed by patterning the second polysilicon layer.
As shown at the right side of FIG. 3C, a first ion implantation mask 320 is formed on the semiconductor substrate of the peripheral circuit unit. As depicted at the left side of FIG. 3C, ions are implanted in order to form a source 308 and a drain 309 of the memory cell unit.
Thereafter, the first ion implantation mask 320 is removed. As shown at the left side of FIG. 3D, a second ion implantation mask 330 is formed on the semiconductor substrate of the memory cell unit, and as shown at the right side of FIG. 3D, impurity ions are implanted into the semiconductor substrate 300 at both sides of the gate electrode 307b of the peripheral circuit unit, thereby forming a lightly-doped region 310 which is called LDD.
The second ion implantation mask 330 is removed. As illustrated in FIG. 3E, sidewall spacers 311 are formed at both side walls of the floating gate electrode 304a and the control gate electrode 307a of the memory cell unit, and the gate electrode 307b of the peripheral circuit unit, respectively.
Thereafter, referring to FIG. 3F, a common source mask 340 is formed on the semiconductor substrate of the memory cell unit and the peripheral circuit unit in order to form a common source. A common source etching is performed by using the common source mask 340, in order to remove the field oxide film which electrically divides the sources of the memory cell. Impurity ions are highly doped into the common source region, thereby forming a common source 308a. 
A third ion implantation mask 350 is formed on the semiconductor substrate of the memory cell unit. As shown at the right side of FIG. 3G, impurity ions are implanted into the semiconductor substrate at both sides of the sidewall spacers of the peripheral circuit unit, thereby forming a source and a drain 312. As described above, a transistor of the peripheral circuit unit of the flash memory device generally has a source/drain structure having a lightly doped drain (LDD) region. The structure is symmetric in the source and drain shape and doping concentration. On the other hand, the source/drain structure of the memory cell unit of the flash memory device is not the LDD structure. Here, the source and drain is asymmetric in concentration and structure, differently from the source/drain structure of the peripheral circuit unit. As a result, in accordance with the fabrication method of the flash memory device, after the source and drain of the cell array unit are formed, the source and drain of the peripheral circuit unit are separately formed, and thus the whole process is complicated.